1. Field of the Invention
The disclosed invention relates to solid-state image sensors and more particularly to small pixel size CMOS image sensors with both global and rolling shutter capability that incorporate BCMD transistors in the pixels with lateral or vertical reset for charge storage and sensing.
2. Description of Related Art
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of an integration cycle collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In CMOS image sensors the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage signal can also be converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically a source follower (SF), which drives the sense lines that are connected to the pixels by suitable addressing transistors. After charge to voltage conversion is completed and the resulting signal transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) as the charge detection node, the reset is accomplished by momentarily turning on a reset transistor that conductively connects the FD node to a voltage reference, which is typically the pixel drain node. This step removes collected charge. However, it generates kTC—reset noise as is well known in the art. kTC noise has to be removed from the signal by the Correlated Double Sampling (CDS) signal processing technique in order to achieve the desired low noise performance. The typical CMOS sensors that utilize the CDS concept usually require four transistors (4T) in each pixel. An example of the 4T pixel circuit with pinned photodiode can be found in U.S. Pat. No. 5,625,210 to Lee, incorporated herein by reference.
In modern CMOS sensor designs the circuitry for several photodiodes may be shared as can found for example in U.S. Pat. No. 6,657,665 B1 to Guidash, which patent is herein incorporated by reference. In this patent the pixel consists of two photodiodes located in neighboring rows that share the same circuitry. Such shared circuit concept can result in having only two metal bus lines in the row direction and two metal bus lines in the column direction per photodiode. The circuit sharing is very useful for designing small pixels or pixels with high Fill Factor (FF) since the spacing and the width of the metal lines essentially determines the minimum pixel size.
The principal disadvantage of the standard CMOS sensors is that pixel scanning after charge has been accumulated in them is performed in a sequential manner row by row. This generates exposure time skew, which can be observed in the pictures of moving objects and which causes an undesirable picture distortion. This method of CMOS sensor scanning is called the “rolling shutter” mode and it resembles the action of the focal plane slit shutter in the old photographic film cameras. In most applications, however it is preferable to expose all the pixels of the image at the same time without the skew and thus eliminate the distortion of moving objects. This type of sensor operation is called the “global shuttering”, which resembles the operation of a mechanical iris shutter in the film cameras. In order to implement this kind of global shuttering it is necessary to provide another charge storage site in the pixels. After charge is integrated in the photodiodes of the pixels it is transferred to the pixel storage sites simultaneously in all the pixels of the array where it can wait for the scanning in the row by row fashion. The pixel scanning time skew is thus independent of the frame pixel exposure time. There have been several methods published in the literature regarding how to incorporate an additional charge storage site into the CMOS sensor pixels. One recent publication is described in ISSCC Digest of Technical Papers pp. 398, 399, by Keita Yasutomi, Shinya Itoh, Shoji Kawahito entitled: “A 2.7e Temporal Noise 99.7% Shutter Efficiency 92 dB Dynamic Range CMOS Image Sensor with Dual Global Shutter Pixels”, is a modification of the well known Interline Transfer CCD concept where charge from the pixel photodiodes is transferred first into vertical CCD registers located in the spaces between the pixels and then from there transferred in parallel fashion row by row into the serial register followed by the CCD transfer out into the common single amplifier. The application of the CCD charge transfer concept into a CMOS sensor to implement the global shutter mode is shown in FIG. 1.
The drawing 100 of FIG. 1 represents a simplified circuit diagram of a pixel of a CMOS sensor that has the global shuttering capability. After charge integration is completed in the pinned photodiode 101 it is transferred via the transfer gate transistor 103 into a second pinned photodiode 102 where it waits for scanning. The charge transfer from the first to the second pinned photodiode is completed in a CCD fashion without generating kTC noise. It is also necessary that the second pinned photodiode 102 has a higher pinning voltage than the first pinned photodiode 101 or the transfer gate 103 has a potential barrier and a well incorporated therein. It is also necessary that the second charge storage pinned photodiode 102 be well shielded from impinging photons 115 to prevent undesirable smear effects when the objects in the scene move. The signal charge readout from the second pinned photodiode 102 then proceeds in the standard way by first resetting the Floating Diffusion (FD) node 104 to the drain bias voltage by momentarily turning on the reset transistor 106 followed by pulsing the charge transfer transistor gate 105. This sequence can now proceed in a sequential order row by row. The signal appearing at the FD node 104 is buffered by the source follower transistor 107 that is addressed by a row addressing transistor 108. The signals to the charge transfer transistor gates 103 and 105, reset transistor 106, and the addressing transistor 108 are supplied by the row bus lines 111, 112, 113, and 114 respectively. The Vdd bias is supplied to the pixels by the column Vdd line 109 and the signal output appears on the column output line 110. Using the pinned photodiodes for charge storage is advantageous since it is well known that these diodes have a low dark current generation. High dark current in the storage sites would also add to noise and also would generate undesirable shading effects in the picture that would have to be compensated for. Unfortunately, the second pinned photodiode consumes a significant valuable pixel area, thus increasing the size of the sensor and ultimately its cost. It is thus desirable to investigate other possibilities of how to build CMOS sensors with the global shuttering capability that consume less pixel area and do not sacrifice the pixel performance. One possibility described in this disclosure is using the BCMD transistor as a charge storage and signal buffer amplifier.
An advantage of the BCMD concept is that only one transistor is used for the pixel addressing, charge sensing including the signal buffering, and charge reset. A description of the BCMD concept can be found in U.S. Pat. No. 5,424,223 and U.S. Pat. No. 4,901,129, both to Hynecek, and both patents are herein incorporated by reference. In the BCMD concept pixel charge is stored under the MOS transistor channel and modulates the transistor threshold. A change in the threshold voltage is sensed when a current is directed to flow through this transistor. After charge sensing has been completed the pixel needs to be reset by removing collected charge. In the original single transistor BCMD concept charge was removed from the pixel in a vertical direction. The BCMD pixel using additional reset structure to provide charge reset in a lateral (horizontal) direction has been developed previously, which has an advantage in Back Side Illuminated (BSI) applications. The BCMD lateral reset removes charge from the pixel completely without kTC noise generation, which is another advantage of this concept. The lateral reset is described in more detail in U.S. Pat. No. 5,424,223 to Hynecek. Another alternate of the BCMD lateral pixel reset is shown in FIG. 2.
In the drawing 200 of FIG. 2 is a simplified cross section of a pixel that consists of a pinned photodiode (PD) and a BCMD charge sensing transistor. A p+ substrate 201 has an epitaxial (epi) p− doped layer 202 deposited thereon. An active region of the pixel is defined by an STI trench 209 that is completely filled by oxide. Another oxide layer 208 covers the entire surface of the pixel array except for contact openings. A p+ layer 204 covers the surface of the PD and extends along the sides of the STI trenches to the bottom of the STI. Another p+ layer 210 is positioned below the BCMD transistor to prevent the photo generated electrons 207 from flowing into the transistor. The photo generated charge 206 accumulates in the n type doped region 205. After completion of integration the charge is transferred from the PD under the BCMD gates 212 that encircles the p+ type doped BCMD source 216. The charge transfer is accomplished by momentarily pulsing the transfer gate 211 positive. The transferred charge under the BCMD gate 212 accumulates in regions 215 where it causes change in the BCMD transistor threshold. This change is the signal that is sensed and processed by the sensor circuits. The reset of the BCMD transistor is accomplished by completely removing charge from the regions 215 and thus restoring the original BCMD transistor threshold without generating any kTC noise. The charge removal is initiated by momentarily pulsing the reset gate 213 positive. The charge transfer pulses to the BCMD transistor and its reset can have independent timing from the pixel integration and addressing thus allowing multiple sensing of the BCMD transistor potential at various times thereby reducing the readout noise. Charge from the BCMD transistor flows into the n+ type doped drain 214 that is biased at Vdd potential. The pulses are supplied to the transfer gate 211, BCMD gate 212 and the reset transistor gate 213 via the row bus lines 219, 220, and 218 respectively. The signal appears at the source of the BCMD transistor 216 and is bussed by the column sense lines 217 to the signal processing circuits located at the periphery of the array. The Vdd potential is supplied to the pixel drain 214 via the column bus line 221.
An advantage of using the BCMD structure in the CMOS sensors that have the global shutter capability in comparison to the non-BCMD prior art is that the charge storage and sensing is accomplished in the same structure, which saves valuable pixel area. Another advantage is that the charge sensing is nondestructive, so no kTC noise is generated. It is thus possible to reverse the order of the double sampling for transistor threshold subtraction without the necessity of correlation to charge transfer from the photodiode. The empty BCMD potential can be sensed after charge has been removed from it, since this potential is identical with the potential before charge has been transferred into the BCMD.